Browsing by Author "Joyce, J."

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    THE MOSSIM SPECIFICATION OF THE SECD DESIGN
    (1989-06-01) Birtwistle, G.; Joyce, J.
    This report gives a complete switch level description of an SECD chip. The notation used is CDL (Circuit Description Language), which is a high level interface to a switch level simulator called Mossim. We give this full documentation in the hope that it can be used as a testbed by others interested in such issues as design for test and formal verification.
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    THE SECD MACHINE ON A CHIP
    (1989-06-01) Birtwistle, G.; Graham, B.; Joyce, J.; Williams, S.; Brinsmead, M.; Keefe, M.; Kroeker, W.; Liblong, B.; Vollmerhaus, W.
    We describe work completed on the design, informal specification, and layout of a custom SECD machine. The chip contains around 25,000 transistors excluding memory cells. The work is part of a long term project which aims to support specification based VLSI design, build a library of cell and sub-system specifications, and investigate algorithms for transforming from specifications to other views.