Browsing by Author "Rakai, Logan M."

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    A Machine Learning Predictor and Corrector Framework to Identify and Resolve VLSI Routing Short Violations
    (2018-10-24) Fakheri Tabrizi, Aysa; Behjat, Laleh; Rakai, Logan M.; Yanushkevich, Svetlana N.; Dimitrov, Vassil
    The growth of Very Large Scale Integration (VLSI) technology provokes new challenges in design automation of Integrated Circuits (ICs). Routability is one of the most challenging aspects in Electronic Design Automation (EDA) that is faced in two consecutive phases of physical design: placement and routing. During placement, the exact locations of circuit components are determined. During routing the paths for all of the wires are specified. Routing is performed in two stages: global routing and detailed routing. Many of the violations that occur during the detailed routing stage stem from ignoring the routing rules during placement. Therefore, detecting and preventing routing violations in the placement stage has become critical in reducing the design time and the possibility of failure. In this thesis, Eh?Predictor, a deep learning framework to predict detailed routing short violations during placement is proposed. In the development of this predictor, relevant features, contributing to routing violations, were identified, extracted, and analyzed. A neural network model that can handle imbalanced data was customized to detect these violations using the defined features. The proposed predictor can be integrated into a placement tool and be used as a guide during the placement process to reduce the number of shorts happening in the detailed routing stage. One of the advantages of this technique is that by using the proposed deep learning-based predictor, global routing is no longer required as frequently. Hence the total runtime for place and route can be significantly reduced. In addition to Eh?Predictor, a detailed routing-aware detailed placement algorithm is developed to improve detailed routability in a relatively short runtime. The proposed technique is referred to as Detailed Routing-aware Detailed Placer (DrDp). DrDp is a heuristic that aims to reduce the local congestion and mitigate routing failure by aligning the connected cells where possible at the final stage of detailed placement process. Experimental results show that Eh?Predictor is able to predict on average 90% of the short violations of previously unseen data with only 5% false alarm rate and considerably reduce computational time, and DrDp can effectively improve the detailed routing quality in a short runtime with no significant change in detailed placement score or total wirelength.
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    Cost and Performance Optimization for Cloud-Based Web Applications Deployment
    (2018-08-21) Mireslami, Seyedehmehrnaz; Far, Behrouz H.; Wang, Mea; Rakai, Logan M.; Moussavi, Mahmood
    Cloud computing offers a pool of various cloud resources, including scalable computing instances, database instances, storage, network bandwidth, etc. which are delivered to customers in an on-demand or reserved manner. In recent years, cloud computing has become a major enablement for businesses and researchers to reduce the deployment costs by externalizing their resources in the cloud environment. Achieving an optimal set of cloud resources for web application deployment among different public cloud providers is a challenge that becomes more difficult when cloud customers tend to optimize both deployment costs and Quality of Service (QoS). Furthermore, due to lack of understanding of the pricing model and the cloud IaaS, a customer may pay more than necessary or may not fully utilize the purchased resources. In this thesis, to tackle these challenges, first, a QoS-aware cost optimization algorithm is proposed that finds the most cost-effective cloud resources for web application deployment. The proposed algorithm maps the minimum required resources for the web application to minimize the deployment costs according to the price model set by the cloud providers. In the next stage, a multi-cloud datacenters cost optimization algorithm is proposed to distribute the cloud resources in different cloud datacenters to improve the web application availability and maintain QoS for geographically distributed user demands. To solve the cloud-based deployment problem from the cloud customer’s point of view, it is vital to balance the two conflicting objectives of deployment costs and QoS performance. Therefore, in this research, a multi-objective optimization algorithm is proposed that minimizes cost and maximizes QoS performance simultaneously by providing a balanced trade-off. Finally, a hybrid method to allocate resources according to the dynamic user demands is developed which includes the reservation and dynamic provision phases. The total deployment cost of each phase is formulated as the optimization objective and a stochastic optimization approach is developed to model the uncertainties in the user demands as random variables.
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    Development of an Accurate Clock Delay Model with Application in Clock Network Buffer Sizing
    (2019-08-09) Farshidi, Ali; Behjat, Laleh; Rakai, Logan M.; Dimitrov, Vassil; Yanushkevich, Svetlana N.
    Clock network synthesis is an important stage of the Integrated Circuit (IC) design cycle. The performance of the IC highly depends on the clock network synthesis which makes this stage critical where accuracy is very important. In this thesis, a new delay model is proposed for clock networks that is capable of estimating clock signal delay with significantly improved accuracy in a relatively low runtime. This model is developed using Least square fitting by employing data oriented training. The developed model is formulated in the form of posynomials which makes it a suitable option for application in geometric programming gate and clock network sizing optimization frameworks. The experimental results demonstrate the effectiveness of the proposed delay model in predicting the delay at the timing critical clock sinks in the clock network, i.e. sinks with minimum and maximum delays, and the estimated values are, on average, 20 ps closer than the Elmore values to the reference circuit simulator tool, ngspice. This is while the runtime of the proposed delay model is negligible compared to the ngspice simulations. This helps designers obtain accurate delay estimations in low runtime for quick optimization iterations. In addition, a clock network buffer sizing approach is developed which includes an objective function with geometric programming format considering two competing objectives, power consumption and clock skew. The clock slew and technology constraints are also integrated into this optimization problem. The clock network buffer sizing experiments show significant improvements compared to the initial clock networks in terms of clock skew, up to 183 ps, while the power consumption improves for all test cases, on average by 54%.