Modern VLSI Placement Observing Technology Constraints

Simple item page
atmire.migration.oldid5654
dc.contributor.advisorBehjat, Laleh
dc.contributor.advisorWestwick, David T
dc.contributor.authorKarimpour Darav, Nima
dc.contributor.committeememberMadden, Patrick H
dc.contributor.committeememberKennings, Andrew Albert
dc.contributor.committeememberRakai, Logan Marshall
dc.contributor.committeememberYanushkevich, Svetlana
dc.contributor.committeememberDimitrov, Vassil Simeonov
dc.date.accessioned2017-05-30T19:19:45Z
dc.date.available2017-05-30T19:19:45Z
dc.date.issued2017
dc.date.submitted2017en
dc.description.abstractThe placement process is a key step in physical design as it directly impacts circuit performance, area, power consumption, reliability, and the quality of other steps, such as routing, in the physical design flow. The placement problem has become ever more complex and challenging due to a wide variety of intricate constraints and design rules imposed by modern technology processes on the Very Large Scale Integration (VLSI) design process. Any constraint not only makes the placement problem challenging; but also can degrade the quality of the objectives optimized during the placement process or other steps in the physical design flow. In addition, with increases in complicated constraints and in the number of circuit components, the runtime and scalability of algorithms used in the placement process has become critical. In this thesis, a high-performance modern technology-driven placer called Eh?Placer is presented to address the challenges rising in modern technology processes. Eh?Placer is a comprehensive placement framework that provides solutions while observing modern technology constraints and routability, and optimizing wire length. Addressing the sheer number of circuit components using parallel computing methods makes Eh?Placer one of the fastest placement tools. In addition to Eh?Placer, a robust and fast legalization framework developed for standard-cell placement is presented. The proposed framework effectively legalizes input placements while minimizing the maximum and average cell movements using a novel global network-flow based approach. In addition, the developed legalizer is the only network flow based approach to observe modern technology constraints. In contrast to the traditional network flow based legalizers, areas with high cell utilization are legalized by finding several candidate paths where there is no need for the post-process step. The proposed legalizer is scalable and robust with respect to the floorplan complexity.en_US
dc.identifier.citationKarimpour Darav, N. (2017). Modern VLSI Placement Observing Technology Constraints (Doctoral thesis, University of Calgary, Calgary, Canada). Retrieved from https://prism.ucalgary.ca. doi:10.11575/PRISM/26969en_US
dc.identifier.doihttp://dx.doi.org/10.11575/PRISM/26969
dc.identifier.urihttp://hdl.handle.net/11023/3858
dc.language.isoeng
dc.publisher.facultyGraduate Studies
dc.publisher.institutionUniversity of Calgaryen
dc.publisher.placeCalgaryen
dc.rightsUniversity of Calgary graduate students retain copyright ownership and moral rights for their thesis. You may use this material in any way that is permitted by the Copyright Act or through licensing that has been assigned to the document. For uses that are not allowable under copyright legislation or licensing, you are required to seek permission.
dc.subjectComputer Science
dc.subjectEngineering--Electronics and Electrical
dc.subject.otherPlacement
dc.subject.otherVLSI
dc.subject.otherNetwork Flow
dc.subject.otherLegalization
dc.subject.otherEh?Placer
dc.subject.otherPhysical Design
dc.subject.otherOptimization Problems
dc.titleModern VLSI Placement Observing Technology Constraints
dc.typedoctoral thesis
thesis.degree.disciplineElectrical and Computer Engineering
thesis.degree.grantorUniversity of Calgary
thesis.degree.nameDoctor of Philosophy (PhD)
ucalgary.item.requestcopytrue
Files
Collections
Open Theses and Dissertations