Self-timed bit-serial architectures for digital signal processing

dc.contributor.advisor	Turner, Laurence E.
dc.contributor.author	Li, Jianchuan
dc.date.accessioned	2017-12-18T21:02:33Z
dc.date.available	2017-12-18T21:02:33Z
dc.date.issued	2005
dc.description	Bibliography: p. 91-95	en
dc.format.extent	xi, 95 leaves : ill. ; 30 cm.	en
dc.identifier.citation	Li, J. (2005). Self-timed bit-serial architectures for digital signal processing (Master's thesis, University of Calgary, Calgary, Canada). Retrieved from https://prism.ucalgary.ca. doi:10.11575/PRISM/156	en_US
dc.identifier.doi	http://dx.doi.org/10.11575/PRISM/156
dc.identifier.uri	http://hdl.handle.net/1880/101157
dc.language.iso	eng
dc.publisher.institution	University of Calgary	en
dc.publisher.place	Calgary	en
dc.rights	University of Calgary graduate students retain copyright ownership and moral rights for their thesis. You may use this material in any way that is permitted by the Copyright Act or through licensing that has been assigned to the document. For uses that are not allowable under copyright legislation or licensing, you are required to seek permission.
dc.title	Self-timed bit-serial architectures for digital signal processing
dc.type	master thesis
thesis.degree.discipline	Electrical and Computer Engineering
thesis.degree.grantor	University of Calgary
thesis.degree.name	Master of Science (MSc)
ucalgary.thesis.accession	Theses Collection 58.002:Box 1589 520492106
ucalgary.thesis.notes	UARC	en
ucalgary.thesis.uarcrelease	y	en

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