Development of an Accurate Clock Delay Model with Application in Clock Network Buffer Sizing

Farshidi, Ali

Development of an Accurate Clock Delay Model with Application in Clock Network Buffer Sizing

dc.contributor.advisor	Behjat, Laleh
dc.contributor.advisor	Rakai, Logan M.
dc.contributor.author	Farshidi, Ali
dc.contributor.committeemember	Dimitrov, Vassil
dc.contributor.committeemember	Yanushkevich, Svetlana N.
dc.date	2019-11
dc.date.accessioned	2019-08-12T17:05:09Z
dc.date.available	2019-08-12T17:05:09Z
dc.date.issued	2019-08-09
dc.description.abstract	Clock network synthesis is an important stage of the Integrated Circuit (IC) design cycle. The performance of the IC highly depends on the clock network synthesis which makes this stage critical where accuracy is very important. In this thesis, a new delay model is proposed for clock networks that is capable of estimating clock signal delay with significantly improved accuracy in a relatively low runtime. This model is developed using Least square fitting by employing data oriented training. The developed model is formulated in the form of posynomials which makes it a suitable option for application in geometric programming gate and clock network sizing optimization frameworks. The experimental results demonstrate the effectiveness of the proposed delay model in predicting the delay at the timing critical clock sinks in the clock network, i.e. sinks with minimum and maximum delays, and the estimated values are, on average, 20 ps closer than the Elmore values to the reference circuit simulator tool, ngspice. This is while the runtime of the proposed delay model is negligible compared to the ngspice simulations. This helps designers obtain accurate delay estimations in low runtime for quick optimization iterations. In addition, a clock network buffer sizing approach is developed which includes an objective function with geometric programming format considering two competing objectives, power consumption and clock skew. The clock slew and technology constraints are also integrated into this optimization problem. The clock network buffer sizing experiments show significant improvements compared to the initial clock networks in terms of clock skew, up to 183 ps, while the power consumption improves for all test cases, on average by 54%.	en_US
dc.identifier.citation	Farshidi, A. (2019). Development of an Accurate Clock Delay Model with Application in Clock Network Buffer Sizing (Master's thesis, University of Calgary, Calgary, Canada). Retrieved from https://prism.ucalgary.ca.	en_US
dc.identifier.doi	http://dx.doi.org/10.11575/PRISM/36801
dc.identifier.uri	http://hdl.handle.net/1880/110709
dc.language.iso	eng	en_US
dc.publisher.faculty	Schulich School of Engineering	en_US
dc.publisher.institution	University of Calgary	en
dc.rights	University of Calgary graduate students retain copyright ownership and moral rights for their thesis. You may use this material in any way that is permitted by the Copyright Act or through licensing that has been assigned to the document. For uses that are not allowable under copyright legislation or licensing, you are required to seek permission.	en_US
dc.subject	Very Large Scale Integration	en_US
dc.subject	Clock Network Buffer Sizing	en_US
dc.subject	VLSI	en_US
dc.subject	Delay Modeling	en_US
dc.subject	Geometric Programming	en_US
dc.subject.classification	Engineering--Electronics and Electrical	en_US
dc.title	Development of an Accurate Clock Delay Model with Application in Clock Network Buffer Sizing	en_US
dc.type	master thesis	en_US
thesis.degree.discipline	Engineering – Electrical & Computer	en_US
thesis.degree.grantor	University of Calgary	en_US
thesis.degree.name	Master of Science (MSc)	en_US
ucalgary.item.requestcopy	true	en_US