Precise Delay Estimation and Compensation for Real-time Adaptive Digital Predistortion
Date
2018-05-17
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Abstract
Real-time implementation of digital predistortion (DPD), a technique for linearizing power amplifiers, has gained importance recently due to stringent transceiver performance specifications for future wireless networks. Precise delay estimation and alignment is imperative for any DPD algorithm to work. Several algorithms are present in the literature on the topic. However, the difficulties arise from energy efficiency and the low-cost implementation of these algorithms. The goal of this work is to implement real-time delay alignment of high bandwidth signals for transmitter impairment compensation in systems using low sampling rate analog-to-digital converters (ADCs). The proposed system uses a resource efficient and scalable design which is based on correlation and fractional delay filters, which can be implemented in the hardware and seamlessly integrated with any DPD system. Both simulation and hardware results, on field programmable gate arrays (FPGAs), have shown improvement in DPD performance when the delay estimation system is employed.
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Keywords
fractional delay estimation, alignment, digital predistortion, power amplifiers, FPGA
Citation
Rafay, A. (2018). Precise Delay Estimation and Compensation for Real-time Adaptive Digital Predistortion (Master's thesis, University of Calgary, Calgary, Canada). Retrieved from https://prism.ucalgary.ca. doi:10.11575/PRISM/31935