THE ARCHITECTURE OF HENDERSON'S SECD MACHINE
Date
1989-01-01
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Abstract
We explain and document the architecture of an eager SECD machine
devised by Henderson. A software interpreter for this architecture
has been in use for two years and has been well tested. Expansion of
the interpreter leads to the detailed specifications of an architecture
in VLSI. Such an SECD chip has been layed out and fabricated.
Description
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Computer Science