Investigating Automatic Bug Repair Using Large Language Models for Digital Hardware Design
Date
2025-01-13
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Abstract
Register-transfer level ( RTL) bugs present critical challenges, impacting the functional correctness, security, and performance of System-on-Chip (SoC) designs. Detecting and repairing RTL bugs is traditionally a time-consuming process requiring skilled engineers, which significantly prolongs SoC development cycles and reduces vendor competitiveness. Given this complexity, there is a strong need for automated repair solutions capable of efficiently addressing RTL bugs to accelerate development timelines. In this thesis, we propose an automated framework leveraging a large language model (LLM) to repair RTL functional bugs. We explore various prompting techniques, including zero-shot, few-shot, and feedback approaches. Zero-shot relies solely on the LLM ’s pretrained knowledge, few-shot provides specific examples of RTL bug repairs, and feedback iteratively refines the LLM’s responses using outputs from prior iterations. Additionally, we investigate six prompting strategies, each incorporating varying levels of context to guide the LLM in the repair process. Our proposed framework operates on benchmarks without requiring prior knowledge of the bug’s type, location, or specific repair steps, better reflecting real-world scenarios than previous approaches. Results demonstrate the potential of LLM -driven automation, with the feedback approach achieving the highest repair success rate by fixing 26 out of 32 benchmarks (81.25%), while the best zero-shot and few-shot strategies repaired 23 out of 32 benchmarks (71.88%). These findings highlight the ability of current LLMs to consistently address RTL functional bugs, offering significant promise for streamlining SoC development by reducing the time and effort required for RTL bug detection and repair.
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Keywords
Verilog, Large Language Model (LLM), Hardware, Bug Repair
Citation
Elnaggar, A. (2025). Investigating automatic bug repair using large language models for digital hardware design (Master's thesis, University of Calgary, Calgary, Canada). Retrieved from https://prism.ucalgary.ca.