Investigating Automatic Bug Repair Using Large Language Models for Digital Hardware Design
| dc.contributor.advisor | Tan, Benjamin | |
| dc.contributor.author | Elnaggar, Abdelrahman | |
| dc.contributor.committeemember | De Carli, Lorenzo | |
| dc.contributor.committeemember | Ginde, Gouri | |
| dc.date | 2025-02 | |
| dc.date.accessioned | 2025-01-16T15:36:56Z | |
| dc.date.available | 2025-01-16T15:36:56Z | |
| dc.date.issued | 2025-01-13 | |
| dc.description.abstract | Register-transfer level ( RTL) bugs present critical challenges, impacting the functional correctness, security, and performance of System-on-Chip (SoC) designs. Detecting and repairing RTL bugs is traditionally a time-consuming process requiring skilled engineers, which significantly prolongs SoC development cycles and reduces vendor competitiveness. Given this complexity, there is a strong need for automated repair solutions capable of efficiently addressing RTL bugs to accelerate development timelines. In this thesis, we propose an automated framework leveraging a large language model (LLM) to repair RTL functional bugs. We explore various prompting techniques, including zero-shot, few-shot, and feedback approaches. Zero-shot relies solely on the LLM ’s pretrained knowledge, few-shot provides specific examples of RTL bug repairs, and feedback iteratively refines the LLM’s responses using outputs from prior iterations. Additionally, we investigate six prompting strategies, each incorporating varying levels of context to guide the LLM in the repair process. Our proposed framework operates on benchmarks without requiring prior knowledge of the bug’s type, location, or specific repair steps, better reflecting real-world scenarios than previous approaches. Results demonstrate the potential of LLM -driven automation, with the feedback approach achieving the highest repair success rate by fixing 26 out of 32 benchmarks (81.25%), while the best zero-shot and few-shot strategies repaired 23 out of 32 benchmarks (71.88%). These findings highlight the ability of current LLMs to consistently address RTL functional bugs, offering significant promise for streamlining SoC development by reducing the time and effort required for RTL bug detection and repair. | |
| dc.identifier.citation | Elnaggar, A. (2025). Investigating automatic bug repair using large language models for digital hardware design (Master's thesis, University of Calgary, Calgary, Canada). Retrieved from https://prism.ucalgary.ca. | |
| dc.identifier.uri | https://hdl.handle.net/1880/120458 | |
| dc.language.iso | en | |
| dc.publisher.faculty | Graduate Studies | |
| dc.publisher.institution | University of Calgary | |
| dc.rights | University of Calgary graduate students retain copyright ownership and moral rights for their thesis. You may use this material in any way that is permitted by the Copyright Act or through licensing that has been assigned to the document. For uses that are not allowable under copyright legislation or licensing, you are required to seek permission. | |
| dc.subject | Verilog | |
| dc.subject | Large Language Model (LLM) | |
| dc.subject | Hardware | |
| dc.subject | Bug Repair | |
| dc.subject.classification | Engineering--Electronics and Electrical | |
| dc.title | Investigating Automatic Bug Repair Using Large Language Models for Digital Hardware Design | |
| dc.type | master thesis | |
| thesis.degree.discipline | Engineering – Electrical & Computer | |
| thesis.degree.grantor | University of Calgary | |
| thesis.degree.name | Master of Science (MSc) | |
| ucalgary.thesis.accesssetbystudent | I do not require a thesis withhold – my thesis will have open access and can be viewed and downloaded publicly as soon as possible. |