VERIFYING SECD IN HOL
Date
1991-01-01
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Abstract
This paper describes some of the work done at Calgary on
the design of an SECD chip and its verification using the Cambridge HOL proof
assistant. The chip is a physical realization of Henderson's variant
of Landin's abstract architecture to execute the lambda calculus. The
machine uses closures and includes explicit machine instructions to
assist recursion.
The complete proof, which goes from an abstract specification down to the
transistor level, is far too involved to be covered in a single paper. In
this paper, we discuss the SECD architecture and design and trace through
a portion of the proof of correctness of one sequence of the microcode.
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Computer Science