REASONING ABOUT ASYNCHRONOUS DESIGNS IN CCS
Date
1992-11-01
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Abstract
With VLSI technology advancing rapidly, synchronous
designers are finding it difficult to distribute clock signals and maintain
functionality as more circuitry is packed onto chips. Ways out of the
dilemma are to raise the level of abstraction and to use simple and
standard rules of composition. These are amongst the advantages
offered by asynchronous design. For years, designs have been
``verified'' via simulation at various levels. Attention is now being
paid to formal methods which use induction proofs over regular
structures in two steps and give full coverage over all input/output
sequences. This thesis brings the formal methods to bear on the
asynchronous hardware design style. A parallel specification style is
developed which scales well when the number of inputs to a system
increases and a testing style based upon the modal $ mu $-calculus is
proposed to test the consequences of specifications. Several
non-trivial designs are evaluated by this methodology.
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Computer Science