REASONING ABOUT ASYNCHRONOUS DESIGNS IN CCS

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dc.contributor.authorLiu, Yingeng
dc.date.accessioned2008-05-20T23:30:35Z
dc.date.available2008-05-20T23:30:35Z
dc.date.computerscience1999-05-27eng
dc.date.issued1992-11-01eng
dc.description.abstractWith VLSI technology advancing rapidly, synchronous designers are finding it difficult to distribute clock signals and maintain functionality as more circuitry is packed onto chips. Ways out of the dilemma are to raise the level of abstraction and to use simple and standard rules of composition. These are amongst the advantages offered by asynchronous design. For years, designs have been ``verified'' via simulation at various levels. Attention is now being paid to formal methods which use induction proofs over regular structures in two steps and give full coverage over all input/output sequences. This thesis brings the formal methods to bear on the asynchronous hardware design style. A parallel specification style is developed which scales well when the number of inputs to a system increases and a testing style based upon the modal $ mu $-calculus is proposed to test the consequences of specifications. Several non-trivial designs are evaluated by this methodology.eng
dc.description.notesWe are currently acquiring citations for the work deposited into this collection. We recognize the distribution rights of this item may have been assigned to another entity, other than the author(s) of the work.If you can provide the citation for this work or you think you own the distribution rights to this work please contact the Institutional Repository Administrator at digitize@ucalgary.caeng
dc.identifier.department1992-492-30eng
dc.identifier.doihttp://dx.doi.org/10.11575/PRISM/31351
dc.identifier.urihttp://hdl.handle.net/1880/46547
dc.language.isoEngeng
dc.publisher.corporateUniversity of Calgaryeng
dc.publisher.facultyScienceeng
dc.subjectComputer Scienceeng
dc.titleREASONING ABOUT ASYNCHRONOUS DESIGNS IN CCSeng
dc.typeunknown
thesis.degree.disciplineComputer Scienceeng
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