Power and Timing Driven Optimal Gate, Clock Buffer and Clock Wire Sizing in High Performance Digital Integrated Circuits

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dc.contributor.advisorBehjat, Laleh
dc.contributor.advisorWestwick, David
dc.contributor.authorFarshidi, Amin
dc.contributor.committeememberDimitrov, Vassil
dc.contributor.committeememberRakai, Logan
dc.contributor.committeememberYanushkevich, Svetlana
dc.contributor.committeememberAnjos, Miguel
dc.date.accessioned2016-06-27T21:28:13Z
dc.date.available2016-06-27T21:28:13Z
dc.date.issued2016
dc.date.submitted2016en
dc.description.abstractGate sizing and clock buffer and wire sizing are intertwined problems that greatly impact the trade-off between the power consumption and timing metrics of digital integrated circuits. With the increasing demands for mobile devices and low power technologies, the power consumption has become as important as the timing performance for the integrated circuit designers. However, finding a balanced trade-off among these objectives is a complex task that may need time-consuming experiments. On the other hand, in the recent technology nodes, the effects of process variations in the circuit component sizes cannot be neglected. In this thesis, a circuit optimization framework is proposed to handle the competing objectives and solve the multi-objective geometric programming problem by achieving a balanced trade-off between power and timing metrics. The proposed framework is self-tuning meaning that the multi-objective weights are optimally calculated during the optimization procedure without any manual tuning by the designer. In the next stage, robust optimization is employed to develop the robust geometric programming counterpart of the uncertainty-aware self-tuning multi-objective optimization framework. It is proposed to consider the buffer size variations during the optimization process by incorporating an uncertainty model in a robust optimization framework. Then, a smart heuristic for discretization of the solutions of the proposed frameworks is developed that remedies the timing performance degradations due to the discretization. Finally, a guideline is provided for the designers to decide which one of the proposed clock network buffer sizing frameworks is the most appropriate for their design goals.en_US
dc.identifier.citationFarshidi, A. (2016). Power and Timing Driven Optimal Gate, Clock Buffer and Clock Wire Sizing in High Performance Digital Integrated Circuits (Doctoral thesis, University of Calgary, Calgary, Canada). Retrieved from https://prism.ucalgary.ca. doi:10.11575/PRISM/27393en_US
dc.identifier.doihttp://dx.doi.org/10.11575/PRISM/27393
dc.identifier.urihttp://hdl.handle.net/11023/3082
dc.language.isoeng
dc.publisher.facultyEngineering
dc.publisher.facultyGraduate Studies
dc.publisher.institutionUniversity of Calgaryen
dc.publisher.placeCalgaryen
dc.rightsUniversity of Calgary graduate students retain copyright ownership and moral rights for their thesis. You may use this material in any way that is permitted by the Copyright Act or through licensing that has been assigned to the document. For uses that are not allowable under copyright legislation or licensing, you are required to seek permission.
dc.subjectEngineering--Electronics and Electrical
dc.subject.classificationClock networken_US
dc.subject.classificationBuffer sizingen_US
dc.subject.classificationGate sizingen_US
dc.subject.classificationWire sizingen_US
dc.subject.classificationIntegrated circuitsen_US
dc.titlePower and Timing Driven Optimal Gate, Clock Buffer and Clock Wire Sizing in High Performance Digital Integrated Circuits
dc.typedoctoral thesis
thesis.degree.disciplineElectrical and Computer Engineering
thesis.degree.grantorUniversity of Calgary
thesis.degree.nameDoctor of Philosophy (PhD)
ucalgary.item.requestcopytrue
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